While principles and embodiments of the invention will be described with reference to a (high voltage) lateral diffused MOSFET, one skilled in the art will appreciate that the invention is also applicable to other transistors, and it will be clear to one skilled in the art, on considering the present specification, what details would need to be changed when applying the invention to such other transistors.
Integrated circuits in which a control function and a driver function are combined are usually referred to as smart power devices. Smart power devices combine high intelligence with low power dissipation. They typically have power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in their output stages designed to operate at higher voltages (at least more than 15 volt) compared with the normal Complementary Metal Oxide Semiconductor (CMOS) logic voltage of typically 5 volts or less, and they typically have logic devices generally incorporated on the same integrated circuit so that both a driver function and a controller function are provided in a single chip. Smart power ICs find a lot of application, e.g. in liquid crystal displays, electro/mechanical devices, automobile electronic devices etc.
In order to increase the breakdown voltage in a high voltage MOSFET generally an N− drift region is formed in both the source and drain regions to result in a symmetric device, or only in the drain region to result in an asymmetric device. FIG. 1 illustrates a symmetrical LDMOS transistor, which includes a P-well region 10 and an N+ drain region 12 formed in an N− drift region 16. An N+ source region 11 is also formed in an N− drift region 15, both N− drift regions 15 and 16 being formed in the P-well. Current flows laterally from the source region 11 to the drain region 12 when an appropriate control voltage is applied to the gate to form a channel at the surface of the P-well region 10.
The P-well region 10 of the LDMOST is separated from the N+ drain region 12 by an extended lightly doped region known as drift region 16. The source region 11 is similarly separated from P-well 10 by drift region 15. The drift region 16 supports the high voltage applied at the drain 12 in both the on and off state. The (near) vertical p-n junction 5 formed between P-well region 10 and N− drift region 16 causes avalanche breakdown to occur at the surface of the device. Generally, the breakdown voltage of such a device is less than that of a parallel plane p-n diode with similar doping concentration due to electric field crowding near the surface, even if an STI (shallow trench isolation) 17 of dielectric material is inserted in the N− drift region 16 to improve surface breakdown by increasing the length of the path between the drift surfaces and the N+ drain 12. To address this situation the RESURF (Reduced Surface Field) concept has been applied. The concentration of the drift region is chosen according to the RESURF condition so that surface breakdown of such devices is eliminated by enhancing the depletion at the vertical junction 5 between the P-well 10 and the N− drift layer 16. The depletion layer of the parallel plane diode 6 is also increased so that the drift region is fully depleted before the surface electric field reaches a critical breakdown value. Device breakdown then occurs in the bulk at the parallel plane junction 6 formed between p-well 10 and N− drift layer 16. The depletion process is accomplished by controlling the amount of charge carriers in the drift region.
The present inventors have appreciated that the optimum breakdown voltage achieved with RESURF puts a limit on the upper bound of the doping concentration of the drift region and hence the minimum achievable specific ON resistance. According to the RESURF condition the N− drift concentration can be increased by decreasing the RESURF width (the width of the drift overlap channel active ‘A1’) to improve the ON resistance, but this will increase the substrate current during the ON state due to the high concentration of the drift region near the channel, which may worsen the Hot Current Injection (HCI) of the device.